(1) Technical Field
This invention relates in general to structure and shape of solder bumps used in the interconnection of integrated solders. In addition to the process of obtaining the desired structure for enhanced interconnection reliability.
(2) Description of Prior Art
The following four U.S. patents relate to solder bump structures or methods of fabrication.
U.S. Pat. No. 6,156,635 issued Dec. 5, 2000, to Masaharu Mizuta disclosed a method for correcting solder bumps.
U.S. Pat. No. 6,146,984 issued Nov. 14, 2000, to Jacques Leibovitz et. al., discloses a method for obtaining uniform height solder bumps.
U.S. Pat. No. 6,142,361 issued Nov. 7, 2000, to Francis J. Downes et. al., discloses a solder bump assembly method using magnetic force and adhesives.
U.S. Pat. No. 6,211,052B1 issued Apr. 3, 2001, to Warren M. Farnworth discloses a mask pattern process for forming UBM pads and solder bumps.
The advent of VLSI technology in the semiconductor field has created the need for higher interconnection density on the surface of the semiconductor chip or die. These interconnections are used to connect the chip terminals to the next level of package or circuit board. The need for higher density interconnections results from the smaller circuit devices results in higher circuit count per chip. The higher circuit count requires more signal input, and signal output connections. In addition, the higher circuit count requires more power to be delivered to the chip or die requiring more power connections. The need for higher interconnection density has resulted in interconnection techniques such as solder bumps that are capable of utilizing the total area of the chip, thus providing more interconnections per chip. The wire bonding technology which is also used for chip interconnections mainly utilizes the periphery of the chip and is limited to the number of interconnections it can provide for a comparable size chip.
The long term reliability of interconnections is an important aspect of the interconnection technology. The design and method of manufacturing the solder bumps dictates the structure of the solder bumps and their inherent long term reliability.
Solder bumps are created on the semiconductor chips or dies at the semiconductor wafer level prior to dicing into chips or dies. After the circuits are formed on the wafer and insulating oxide layers are deposited, FIG. 110, contact holes to the circuit metallurgy are etched in the insulating layer utilizing photo lithographic techniques. Metallization layers are then created to provide contact to the circuits and allow for the fabrication of solder bumps at the appropriate spots. The metal layers that are deposited usually are referred to as, xe2x80x9cunder ball metallurgyxe2x80x9d, or UBM consist of the following:
A layer of metal 12 that adheres to the circuit metal and the insulating oxide, usually a thin layer 0.1xcx9c0.2 um thickness of titanium (Ti).
A layer of sputtered copper, (Cu) 14.
A layer of plated copper 16, usually 4xcx9c8 um thick, that forms a protective barrier against contamination of the base metallurgy.
Finally, a layer of plated nickel, (Ni) 18, is deposited to allow for adhesion or wetting of the solder, usually a lead tin, (Pbxe2x80x94Sn), alloy.
The lead-tin solder is deposited by plating through holes in a photoresist layer that has been patterned to have openings, circular holes, over the desired contact area. After the photoresist is removed the UBM is etched using the plated solder as a mask. The etching process is performed in several steps. First, the nickel layer is etched, then the thick copper layer, and finally the adhesive titanium layer. In etching the copper layer 16, an undercut results as shown. Due to its thickness, the copper needs to be exposed to the etchant for a longer period resulting in an undercut. The undercut is detrimental to the long term reliability of the interconnection but is an inherent result of the etching process. After a solder reflow step that utilizes flux the resultant structure shown in FIG. 1 is achieved.
Samples of the finished wafers and/or chips are tested for mechanical integrity of the solder bumps by the use of bump shear or die shear tests. These tests have been correlated with long term reliability testing, i.e., thermal cycling to indicate levels of reliability. The main indicator is the location of the bump failure at the shear tests. An acceptable result is when the shear tests result in the majority of the failures in the bulk solder and not at the chip interface.
The objective of the invention is to provide a solder bump comprised of a structure that has a low stress concentration profile.
A further objective of the invention is to provide a method for obtaining a low stress concentration solder ball structure.
Another objective of the invention is to provide a method for obtaining oxide free UBM edges.
An additional objective of the invention is to provide a method wherein the solder of the solder bump contacts the circular edge of the UBM.
In addition, an objective of the present invention is to provide a method to allow the solder of a solder bump to completely fill the undercut of the UBM.
The above objectives are achieved by the present invention by providing a solder bump structure that has a profile free of any discontinuities which would cause high stress concentration factors. One of the main discontinuities that exist in solder bump technology is the resultant undercut of the thick copper layer in the UBM due to the etching process. The present invention achieves a structure that allows the solder of the solder bump to fully cover the sides of the UBM as shown in FIG. 2. FIG. 2 shows that the undercut has been filled in by the solder and provides a low stress solder bump.
The low stress shown in FIG. 2 is achieved by a solder bump reflow process utilizing a rosin type flux to the wafer by spin coating. The wafer is then placed in a reflow oven where the action of the flux removes any oxides present on the edges of the UBM and allows the solder bump to wet the circular edge and flow to the surface of the wafer.